1. Field of the Invention
The present invention relates to microprocessors, and more particularly, to apparatus for controlling the movement of data to and from a slave coprocessor.
2. Description of the Prior Art
In U.S. Pat. No 4,442,484 of Robert Childs, Jr., et al entitled "Microprocessor Memory Management and Protection Mechanism," granted on Apr. 10, 1984, and assigned to a common assignee, Intel Corp., there is described a memory management and protection mechanism in which access to protected entitites is controlled. The memory-protection mechanism provides protection of a task from other tasks, protection of a segment at one level from any task at a less privileged level, and immediate detection of attempted protection violations.
It is desirable to utilize the microprocessor described in the Childs, et al patent application as a master microprocessor with a slave coprocessor, such as an 8087 Math Processor, with the coprocessor being subject to the same protection rules as the master microprocessor. In order to do this, it is necessary to provide an interface which will allow the transfer of operands between the attached coprocessor and main memory without circumventing the protection mechanism in the microprocessor.
Prior to the development of large-scale integration (LSI) technology, the interfaces between computer components were mainly concerned with transferring data at the highest speed possible commensurate with the electrical characteristics of the cables between the units and the electronic circuits which drive signals on the cables. The use of these prior interfaces with LSI microprocessors is prohibitive because there are not enough input/output pins available on the LSI package with present-day technology. An LSI microprocessor has to use fewer actual lines interconnecting the modules, but still meet the requirement of being able to handle data movement and control operations just as complex as those of previous data processing systems.
It is therefore a primary object of this invention to provide an interface between a master microprocessor and a slave coprocessor which utilizes a minimum number of input/output pins and which does not circumvent the memory-protection mechanism of the master microprocessor.